Lately, a high density is promoted in a semiconductor mounting technology to realize high functionality, enhanced performance, and downsizing of electronic devices. A wire bonding technology (WB), a tape automated wire bonding (TAB) technology relating to a wireless bonding technology, and a flip chip bonding (FCB) technology are listed as a representative technology of bonding method for bonding semiconductor devices, as well as a semiconductor device and a circuit board. Among them, as the technology to mount in high density semiconductor devices such as computer, the flip chip bonding (FCB) technology enabling the highest density mounting has been widely applied. The flip chip bonding bonds bumps (protruding part) formed on the semiconductor device or the like to the circuit board or the like. The bumps are formed mainly by means of plating process.
According to the plating process for forming bumps, it is possible to form finely patterned bumps. In addition, the height of the bump is intended to be controlled under the various conditions. However, there is a problem in which the height of the bumps is varied to some extent. As the remedy for the variation of the height of the bumps so as to prevent the contact failure of the electrode, the pressure is applied during the bonding in order to closely contact all the bumps. The above described method is possible. However, the excessively applied pressure causes the strain to remain within the bump, and lowers the thermal stress resistance to result in the breakage. Accordingly, the structure of the bump for connecting to the metal fine pattern has preferably soft and flexible structure when the pressure is applied. In addition, the bump formed by means of the plating has a problem in which cracks and fractures are caused supposedly due to the fatigue failure in the process of the usage. In the flip chip bonding (FCB) technology, in case that the material forming the semiconductor device is different from the material forming the circuit wiring board, the stress strain is caused on the solder bump electrode due to the difference of the expansion coefficients. The above described stress strain damages the solder bump electrode to lower a reliable life time.
Patent document 1 discloses a connecting bump used for electrically connecting a conducting wiring circuit on a substrate and other substrate or component, which is formed in such manner that an opening portion is arranged on a substrate with the use of a photosensitive resin, then metal fine particles having mean primary diameter from 0.1 μm to 50 μm is filled therein, and then baked.
Patent document 2 discloses nano porous solder formed in such manner that a nano solder precursor using nano particles is mixed with a foaming agent, then thus prepared mixture is placed on the die, and then the foaming solder precursor is swelled.
Patent document 3 discloses a bump obtained by sintering a metal paste without glass frit, which contains metal powders comprising gold, silver or palladium powder having mean particle diameter from 0.005 to 1.0 μm, and an organic solvent, at a temperature from 200 to 400 degrees C. It is disclosed that when the metal paste without the glass frit is used, the sintered body which is relatively soft and has elasticity can be formed on a semiconductor wafer.
Patent document 4 discloses bumps comprising a Au plating layer provided in a fine hole of a photo resist layer formed on a substrate (first bump layer, height of 10 μm) and a sintered body (a second bump layer) provided on the Au layer, in which Au paste as a metal paste is fallen as a drop and filled, and then sintered to form the sintered body.